Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Processor systems frequently store and access information in cache memory (“cache”). Processor cache generally is significantly faster for writing and reading information than main or system memory. Thus, routines that are time-sensitive or time-critical may be placed in cache. An example of such a routine is an interrupt service routine. If an interrupt service routine is not pulled entirely from cache, such as partly stored in cache and partly stored in system memory, then there are at least two significant negative consequences. Not only is execution of such routine slowed by an increase in latency due to accessing from system memory in comparison to a cache only access, the latency is variable. In other words, there is a latency associated with cache access and one or more other latencies associated with system memory different from the latency associated with cache access. As is known, conventionally cache access latency is fixed for both reads and writes, though not necessarily the same latency for both. While some cache is capable of being locked down to keep information, such as for an interrupt service routine, from leaving the cache, locking down too much cache invalidates or at least significantly diminishes its usefulness.
Another use of cache is for fixed, low latency data access, such as table lookups. However, access to a table conventionally is a “random access,” and thus data may fall out of cache due to stagnation, and be replaced with other cached data more frequently or more recently accessed. Furthermore, a data lookup table may become sufficiently large to the extent that it is not feasible or possible to entirely store it in cache.
As is well known, cache does not store as much information as system memory. However, conventionally a system bus by which system memory is accessed is an arbitrated bus, which makes latency associated with system memory access greater than that associated with cache access. Additionally, such a system bus conventionally runs at a frequency significantly slower than that of the processor clock, and as cache may be operated at the frequency of the processor clock, this too means that access to system memory is slower than access to cache.
In some processor architectures, a cache-like access is provided via a processor-to-memory interface. An example of such a cache-like interface is an On-Chip Memory (“OCM”) interface of a PowerPC processor. A PowerPC processor core is embedded in FPGAs available from Xilinx, Inc. of San Jose, Calif. An OCM interface may be used to provide cache-like access to memory, and such memory may be capable of storing more information than level one cache. However, Virtex-5™ FPGAs with embedded PowerPC processors do not have OCM interfaces such as those available in Virtex-4™ FPGAs with embedded PowerPC processors, for example. As a result, level one cache-like access using an OCM interface is not available on Virtex-5™ FPGAs. Thus, an alternative to cache-like OCM interface access is needed in Virtex-5™ FPGAs.
Accordingly, generally it would be desirable and useful to provide means for cache-like access without having to use an OCM interface.